/*
 * Copyright (c) 2021-2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */


#ifndef HPM_GPU_H
#define HPM_GPU_H

typedef struct {
    __RW uint32_t AQHICLOCKCONTROL;            /* 0x0: clock control register */
    __R  uint32_t AQHILDLE;                    /* 0x4: idle status register */
    __R  uint8_t  RESERVED0[8];                /* 0x8 - 0xF: Reserved */
    __R  uint32_t AQINTRACKNOWLEDGE;           /* 0x10: interrupt acknoledge register */
    __RW uint32_t AQINTRENBL;                  /* 0x14: interrupt enable register */
    __R  uint8_t  RESERVED1[12];               /* 0x18 - 0x23: Reserved */
    __R  uint32_t GCCHIPREV;                   /* 0x24: chip revison register */
    __R  uint32_t GCCHIPDATE;                  /* 0x28: chip date register */
    __R  uint8_t  RESERVED2[108];              /* 0x2C - 0x97: Reserved */
    __R  uint32_t GCREGHICHIPPATCHREV;         /* 0x98: chip patch revision register */
    __R  uint8_t  RESERVED3[12];               /* 0x9C - 0xA7: Reserved */
    __R  uint32_t GCPRODUCTID;                 /* 0xA8: product identification register */
    __R  uint8_t  RESERVED4[84];               /* 0xAC - 0xFF: Reserved */
    __RW uint32_t GCMODULEPOWERCONTROLS;       /* 0x100: module power control register */
    __RW uint32_t GCMODULEPOWERMODULECONTROL;  /* 0x104: module power module control register */
    __R  uint32_t GCMODULEPOWERMODULESTATUS;   /* 0x108: module power module status register */
    __R  uint8_t  RESERVED5[756];              /* 0x10C - 0x3FF: Reserved */
    __RW uint32_t AQMEMORYFEPAGETABLE;         /* 0x400: fetch engine page table base address register */
    __R  uint8_t  RESERVED6[16];               /* 0x404 - 0x413: Reserved */
    __RW uint32_t AQMEMORYDEBUG;               /* 0x414: memory debug register */
    __R  uint8_t  RESERVED7[20];               /* 0x418 - 0x42B: Reserved */
    __RW uint32_t AQREGISTERTIMINGCONTROL;     /* 0x42C: timing control register */
    __R  uint8_t  RESERVED8[208];              /* 0x430 - 0x4FF: Reserved */
    __RW uint32_t GCREGFETCHADDRESS;           /* 0x500: fetch command buffer base address register */
    __RW uint32_t GCREGFETCHCONTROL;           /* 0x504: fetch control register */
    __R  uint32_t GCREGCURRENTFETCHADDRESS;    /* 0x508: current fetch command address register */
} GPU_Type;


/* Bitfield definition for register: AQHICLOCKCONTROL */
/*
 * ISOLATE_GPU (RW)
 *
 * isolate GPU bit, used for power on/off
 */
#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK (0x80000UL)
#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT (19U)
#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT) & GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK)
#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK) >> GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT)

/*
 * IDLE_VG (R)
 *
 * vg pipe is idle
 */
#define GPU_AQHICLOCKCONTROL_IDLE_VG_MASK (0x40000UL)
#define GPU_AQHICLOCKCONTROL_IDLE_VG_SHIFT (18U)
#define GPU_AQHICLOCKCONTROL_IDLE_VG_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE_VG_MASK) >> GPU_AQHICLOCKCONTROL_IDLE_VG_SHIFT)

/*
 * IDLE2_D (R)
 *
 * 2D pipe is idle or not present
 */
#define GPU_AQHICLOCKCONTROL_IDLE2_D_MASK (0x20000UL)
#define GPU_AQHICLOCKCONTROL_IDLE2_D_SHIFT (17U)
#define GPU_AQHICLOCKCONTROL_IDLE2_D_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE2_D_MASK) >> GPU_AQHICLOCKCONTROL_IDLE2_D_SHIFT)

/*
 * IDLE3_D (R)
 *
 * 3D pipe is idle or not present
 */
#define GPU_AQHICLOCKCONTROL_IDLE3_D_MASK (0x10000UL)
#define GPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT (16U)
#define GPU_AQHICLOCKCONTROL_IDLE3_D_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE3_D_MASK) >> GPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT)

/*
 * DISABLE_RAM_POWER_OPTIMIZATION (RW)
 *
 * disables ram power optimization
 */
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK (0x2000U)
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT (13U)
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK)
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT)

/*
 * SOFT_RESET (RW)
 *
 * soft reset the IP
 */
#define GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK (0x1000U)
#define GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT (12U)
#define GPU_AQHICLOCKCONTROL_SOFT_RESET_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT) & GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK)
#define GPU_AQHICLOCKCONTROL_SOFT_RESET_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK) >> GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT)

/*
 * DISABLE_DEBUG_REGISTERS (RW)
 *
 * disable debug registers
 */
#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK (0x800U)
#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT (11U)
#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK)
#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT)

/*
 * DISABLE_RAM_CLOCK_GATING (RW)
 *
 * disables clock gating for rams
 */
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK (0x400U)
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT (10U)
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK)
#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT)

/*
 * FSCALE_CMD_LOAD (RW)
 *
 * core clock frequency scale value enable
 */
#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK (0x200U)
#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT (9U)
#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT) & GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK)
#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK) >> GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT)

/*
 * FSCALE_VAL (RW)
 *
 * core clock frequency scale value
 */
#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK (0x1FCU)
#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT (2U)
#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT) & GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK)
#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK) >> GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT)

/*
 * CLK2D_DIS (RW)
 *
 * disable 2D/VG clock
 */
#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK (0x2U)
#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT (1U)
#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT) & GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK)
#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK) >> GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT)

/* Bitfield definition for register: AQHILDLE */
/*
 * AXI_LP (R)
 *
 * axi is in low power mode
 */
#define GPU_AQHILDLE_AXI_LP_MASK (0x80000000UL)
#define GPU_AQHILDLE_AXI_LP_SHIFT (31U)
#define GPU_AQHILDLE_AXI_LP_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_AXI_LP_MASK) >> GPU_AQHILDLE_AXI_LP_SHIFT)

/*
 * IDLE_BLT (R)
 *
 * BLT is idle or not present
 */
#define GPU_AQHILDLE_IDLE_BLT_MASK (0x1000U)
#define GPU_AQHILDLE_IDLE_BLT_SHIFT (12U)
#define GPU_AQHILDLE_IDLE_BLT_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_BLT_MASK) >> GPU_AQHILDLE_IDLE_BLT_SHIFT)

/*
 * IDLE_TS (R)
 *
 * Tessellation Engine is idle
 */
#define GPU_AQHILDLE_IDLE_TS_MASK (0x800U)
#define GPU_AQHILDLE_IDLE_TS_SHIFT (11U)
#define GPU_AQHILDLE_IDLE_TS_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_TS_MASK) >> GPU_AQHILDLE_IDLE_TS_SHIFT)

/*
 * IDLE_FP (R)
 *
 * FP is idle or not present
 */
#define GPU_AQHILDLE_IDLE_FP_MASK (0x400U)
#define GPU_AQHILDLE_IDLE_FP_SHIFT (10U)
#define GPU_AQHILDLE_IDLE_FP_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_FP_MASK) >> GPU_AQHILDLE_IDLE_FP_SHIFT)

/*
 * IDLE_IM (R)
 *
 * Image Engine is idle
 */
#define GPU_AQHILDLE_IDLE_IM_MASK (0x200U)
#define GPU_AQHILDLE_IDLE_IM_SHIFT (9U)
#define GPU_AQHILDLE_IDLE_IM_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_IM_MASK) >> GPU_AQHILDLE_IDLE_IM_SHIFT)

/*
 * IDLE_VG (R)
 *
 * Vector Graphics Engine is idle
 */
#define GPU_AQHILDLE_IDLE_VG_MASK (0x100U)
#define GPU_AQHILDLE_IDLE_VG_SHIFT (8U)
#define GPU_AQHILDLE_IDLE_VG_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_VG_MASK) >> GPU_AQHILDLE_IDLE_VG_SHIFT)

/*
 * IDLE_TX (R)
 *
 * TX is idle or not present
 */
#define GPU_AQHILDLE_IDLE_TX_MASK (0x80U)
#define GPU_AQHILDLE_IDLE_TX_SHIFT (7U)
#define GPU_AQHILDLE_IDLE_TX_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_TX_MASK) >> GPU_AQHILDLE_IDLE_TX_SHIFT)

/*
 * IDLE_RA (R)
 *
 * RA is idle or not present
 */
#define GPU_AQHILDLE_IDLE_RA_MASK (0x40U)
#define GPU_AQHILDLE_IDLE_RA_SHIFT (6U)
#define GPU_AQHILDLE_IDLE_RA_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_RA_MASK) >> GPU_AQHILDLE_IDLE_RA_SHIFT)

/*
 * IDLE_SE (R)
 *
 * SE is idle or not present
 */
#define GPU_AQHILDLE_IDLE_SE_MASK (0x20U)
#define GPU_AQHILDLE_IDLE_SE_SHIFT (5U)
#define GPU_AQHILDLE_IDLE_SE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_SE_MASK) >> GPU_AQHILDLE_IDLE_SE_SHIFT)

/*
 * IDLE_PA (R)
 *
 * PA is idle or not present
 */
#define GPU_AQHILDLE_IDLE_PA_MASK (0x10U)
#define GPU_AQHILDLE_IDLE_PA_SHIFT (4U)
#define GPU_AQHILDLE_IDLE_PA_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_PA_MASK) >> GPU_AQHILDLE_IDLE_PA_SHIFT)

/*
 * IDLE_SH (R)
 *
 * SH is idle or not present
 */
#define GPU_AQHILDLE_IDLE_SH_MASK (0x8U)
#define GPU_AQHILDLE_IDLE_SH_SHIFT (3U)
#define GPU_AQHILDLE_IDLE_SH_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_SH_MASK) >> GPU_AQHILDLE_IDLE_SH_SHIFT)

/*
 * IDLE_PE (R)
 *
 * Pixel engine is idle
 */
#define GPU_AQHILDLE_IDLE_PE_MASK (0x4U)
#define GPU_AQHILDLE_IDLE_PE_SHIFT (2U)
#define GPU_AQHILDLE_IDLE_PE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_PE_MASK) >> GPU_AQHILDLE_IDLE_PE_SHIFT)

/*
 * IDLE_DE (R)
 *
 * DE is dile or not present
 */
#define GPU_AQHILDLE_IDLE_DE_MASK (0x2U)
#define GPU_AQHILDLE_IDLE_DE_SHIFT (1U)
#define GPU_AQHILDLE_IDLE_DE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_DE_MASK) >> GPU_AQHILDLE_IDLE_DE_SHIFT)

/*
 * IDLE_FE (R)
 *
 * 0: fetch engine is busy  1:fetch engine is idle
 */
#define GPU_AQHILDLE_IDLE_FE_MASK (0x1U)
#define GPU_AQHILDLE_IDLE_FE_SHIFT (0U)
#define GPU_AQHILDLE_IDLE_FE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_FE_MASK) >> GPU_AQHILDLE_IDLE_FE_SHIFT)

/* Bitfield definition for register: AQINTRACKNOWLEDGE */
/*
 * INTR_VEC (R)
 *
 * for each interrupt event, 0=clear,1=interrupt active
 */
#define GPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK (0xFFFFFFFFUL)
#define GPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT (0U)
#define GPU_AQINTRACKNOWLEDGE_INTR_VEC_GET(x) (((uint32_t)(x) & GPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK) >> GPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT)

/* Bitfield definition for register: AQINTRENBL */
/*
 * INTR_ENBL_VEC (RW)
 *
 * 0=disable interrupt; 1=enable interrupt
 */
#define GPU_AQINTRENBL_INTR_ENBL_VEC_MASK (0xFFFFFFFFUL)
#define GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT (0U)
#define GPU_AQINTRENBL_INTR_ENBL_VEC_SET(x) (((uint32_t)(x) << GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT) & GPU_AQINTRENBL_INTR_ENBL_VEC_MASK)
#define GPU_AQINTRENBL_INTR_ENBL_VEC_GET(x) (((uint32_t)(x) & GPU_AQINTRENBL_INTR_ENBL_VEC_MASK) >> GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT)

/* Bitfield definition for register: GCCHIPREV */
/*
 * REV (R)
 *
 * revision
 */
#define GPU_GCCHIPREV_REV_MASK (0xFFFFFFFFUL)
#define GPU_GCCHIPREV_REV_SHIFT (0U)
#define GPU_GCCHIPREV_REV_GET(x) (((uint32_t)(x) & GPU_GCCHIPREV_REV_MASK) >> GPU_GCCHIPREV_REV_SHIFT)

/* Bitfield definition for register: GCCHIPDATE */
/*
 * DATE (R)
 *
 * date
 */
#define GPU_GCCHIPDATE_DATE_MASK (0xFFFFFFFFUL)
#define GPU_GCCHIPDATE_DATE_SHIFT (0U)
#define GPU_GCCHIPDATE_DATE_GET(x) (((uint32_t)(x) & GPU_GCCHIPDATE_DATE_MASK) >> GPU_GCCHIPDATE_DATE_SHIFT)

/* Bitfield definition for register: GCREGHICHIPPATCHREV */
/*
 * PATCH_REV (R)
 *
 * patch revision
 */
#define GPU_GCREGHICHIPPATCHREV_PATCH_REV_MASK (0xFFU)
#define GPU_GCREGHICHIPPATCHREV_PATCH_REV_SHIFT (0U)
#define GPU_GCREGHICHIPPATCHREV_PATCH_REV_GET(x) (((uint32_t)(x) & GPU_GCREGHICHIPPATCHREV_PATCH_REV_MASK) >> GPU_GCREGHICHIPPATCHREV_PATCH_REV_SHIFT)

/* Bitfield definition for register: GCPRODUCTID */
/*
 * TYPE (R)
 *
 * product type is 3:VG
 */
#define GPU_GCPRODUCTID_TYPE_MASK (0xF000000UL)
#define GPU_GCPRODUCTID_TYPE_SHIFT (24U)
#define GPU_GCPRODUCTID_TYPE_GET(x) (((uint32_t)(x) & GPU_GCPRODUCTID_TYPE_MASK) >> GPU_GCPRODUCTID_TYPE_SHIFT)

/*
 * NUM (R)
 *
 * product number is 265
 */
#define GPU_GCPRODUCTID_NUM_MASK (0xFFFFF0UL)
#define GPU_GCPRODUCTID_NUM_SHIFT (4U)
#define GPU_GCPRODUCTID_NUM_GET(x) (((uint32_t)(x) & GPU_GCPRODUCTID_NUM_MASK) >> GPU_GCPRODUCTID_NUM_SHIFT)

/*
 * GRADE_LEVEL (R)
 *
 * 0:None_no extra letter on the product name for this core 1:nano 5:nano ultra
 */
#define GPU_GCPRODUCTID_GRADE_LEVEL_MASK (0xFU)
#define GPU_GCPRODUCTID_GRADE_LEVEL_SHIFT (0U)
#define GPU_GCPRODUCTID_GRADE_LEVEL_GET(x) (((uint32_t)(x) & GPU_GCPRODUCTID_GRADE_LEVEL_MASK) >> GPU_GCPRODUCTID_GRADE_LEVEL_SHIFT)

/* Bitfield definition for register: GCMODULEPOWERCONTROLS */
/*
 * TURN_OFF_COUNTER (RW)
 *
 * counter value for clock gating the module if the module is idle for this amout of clock cycles
 */
#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK (0xFFFF0000UL)
#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT (16U)
#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT) & GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK)
#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK) >> GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT)

/*
 * TURN_ON_COUNTER (RW)
 *
 * number of clock cycle gating the module if the modules is idle for this amout of clockk cycles
 */
#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK (0xF0U)
#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT (4U)
#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT) & GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK)
#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK) >> GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT)

/*
 * DISABLE_STARVE_MODULE_CLOCK_GATING (RW)
 *
 * disable module level clock gating for starve/idle condition
 */
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK (0x4U)
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT (2U)
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK)
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT)

/*
 * DISABLE_STALL_MODULE_CLOCK_GATING (RW)
 *
 * disable module level clock gating for stall condition
 */
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK (0x2U)
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT (1U)
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK)
#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT)

/*
 * ENABLE_MODULE_CLOCK_GATING (RW)
 *
 * enable module level clock gating
 */
#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK (0x1U)
#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT (0U)
#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK)
#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT)

/* Bitfield definition for register: GCMODULEPOWERMODULECONTROL */
/*
 * DISABLE_MODULE_CLOCKGATING_FLEXA (RW)
 *
 * disables module level clock gating for flexa, not supported for all variants
 */
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK (0x1000U)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT (12U)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT)

/*
 * DISABLE_MODULE_CLOCK_GATING_TS (RW)
 *
 * disables module level clock gating for TS
 */
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK (0x800U)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT (11U)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT)

/*
 * DISABLE_MODULE_CLOCK_GATING_IM (RW)
 *
 * disables module level clock gating for IM
 */
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK (0x200U)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT (9U)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT)

/*
 * DISABLE_MODULE_CLOCK_GATING_VG (RW)
 *
 * disables module lelvel clock gating for VG
 */
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK (0x100U)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT (8U)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT)

/*
 * DISABLE_MODULE_CLOCK_GATING_PE (RW)
 *
 * disables module level clock gating for PE
 */
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK (0x4U)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT (2U)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT)

/*
 * DISABLE_MODULE_CLOCK_GATING_FE (RW)
 *
 * disables module level clock gating for FE
 */
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK (0x1U)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT (0U)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK)
#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT)

/* Bitfield definition for register: GCMODULEPOWERMODULESTATUS */
/*
 * MODULE_CLOCK_GATED_FLEXA (R)
 *
 * module level ckock gating is on for flexa
 */
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_MASK (0x1000U)
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_SHIFT (12U)
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_SHIFT)

/*
 * MODULE_CLOCK_GATED_TS (R)
 *
 * module level ckock gating is on for ts
 */
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_MASK (0x800U)
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_SHIFT (11U)
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_SHIFT)

/*
 * MODULE_CLOCK_GATED_IM (R)
 *
 * module level clock gating is on for IM
 */
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_MASK (0x200U)
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_SHIFT (9U)
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_SHIFT)

/*
 * MODULE_CLOCK_GATED_VG (R)
 *
 * module level clock gating is on for VG
 */
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_MASK (0x100U)
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_SHIFT (8U)
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_SHIFT)

/*
 * MODULE_CLOCK_GATED_PE (R)
 *
 * module level clock gating is on for PE
 */
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_MASK (0x4U)
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_SHIFT (2U)
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_SHIFT)

/*
 * MODULE_CLOCK_GATED_FE (R)
 *
 * module level clock gating is on for FE
 */
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_MASK (0x1U)
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_SHIFT (0U)
#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_SHIFT)

/* Bitfield definition for register: AQMEMORYFEPAGETABLE */
/*
 * BASE_ADDRESS (RW)
 *
 * base address for the FE virtual address lookup table
 */
#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK (0xFFFFF000UL)
#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT (12U)
#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SET(x) (((uint32_t)(x) << GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT) & GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK)
#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_GET(x) (((uint32_t)(x) & GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK) >> GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT)

/* Bitfield definition for register: AQMEMORYDEBUG */
/*
 * ZCOMP_LIMIT (RW)
 *
 * not relevant for vector graphics IP
 */
#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK (0x3F000000UL)
#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT (24U)
#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SET(x) (((uint32_t)(x) << GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT) & GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK)
#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_GET(x) (((uint32_t)(x) & GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK) >> GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT)

/*
 * MAX_OUTSTANDING_READS (RW)
 *
 * limits the total number of outstanding read requests
 */
#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK (0xFFU)
#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT (0U)
#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SET(x) (((uint32_t)(x) << GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT) & GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK)
#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_GET(x) (((uint32_t)(x) & GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK) >> GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT)

/* Bitfield definition for register: AQREGISTERTIMINGCONTROL */
/*
 * POWER_DOWN (RW)
 *
 * powerdown memory
 */
#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK (0x100000UL)
#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT (20U)
#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK)
#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK) >> GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT)

/*
 * FAST_WTC (RW)
 *
 * WTC for fast rams
 */
#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK (0xC0000UL)
#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT (18U)
#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK)
#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT)

/*
 * FAST_RTC (RW)
 *
 * RTC for fast rams
 */
#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK (0x30000UL)
#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT (16U)
#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK)
#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT)

/*
 * FOR_RF2P (RW)
 *
 * for 2 port ram
 */
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK (0xFF00U)
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT (8U)
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK)
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT)

/*
 * FOR_RF1P (RW)
 *
 * for 1 port ram
 */
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK (0xFFU)
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT (0U)
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK)
#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT)

/* Bitfield definition for register: GCREGFETCHADDRESS */
/*
 * ADDRESS (RW)
 *
 * address of command buffer
 */
#define GPU_GCREGFETCHADDRESS_ADDRESS_MASK (0xFFFFFFFCUL)
#define GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT (2U)
#define GPU_GCREGFETCHADDRESS_ADDRESS_SET(x) (((uint32_t)(x) << GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT) & GPU_GCREGFETCHADDRESS_ADDRESS_MASK)
#define GPU_GCREGFETCHADDRESS_ADDRESS_GET(x) (((uint32_t)(x) & GPU_GCREGFETCHADDRESS_ADDRESS_MASK) >> GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT)

/*
 * TYPE (RW)
 *
 * 0=system  2=vritual 1=local
 */
#define GPU_GCREGFETCHADDRESS_TYPE_MASK (0x3U)
#define GPU_GCREGFETCHADDRESS_TYPE_SHIFT (0U)
#define GPU_GCREGFETCHADDRESS_TYPE_SET(x) (((uint32_t)(x) << GPU_GCREGFETCHADDRESS_TYPE_SHIFT) & GPU_GCREGFETCHADDRESS_TYPE_MASK)
#define GPU_GCREGFETCHADDRESS_TYPE_GET(x) (((uint32_t)(x) & GPU_GCREGFETCHADDRESS_TYPE_MASK) >> GPU_GCREGFETCHADDRESS_TYPE_SHIFT)

/* Bitfield definition for register: GCREGFETCHCONTROL */
/*
 * COUNT (RW)
 *
 * number of 64bit words to fetch
 */
#define GPU_GCREGFETCHCONTROL_COUNT_MASK (0x1FFFFFUL)
#define GPU_GCREGFETCHCONTROL_COUNT_SHIFT (0U)
#define GPU_GCREGFETCHCONTROL_COUNT_SET(x) (((uint32_t)(x) << GPU_GCREGFETCHCONTROL_COUNT_SHIFT) & GPU_GCREGFETCHCONTROL_COUNT_MASK)
#define GPU_GCREGFETCHCONTROL_COUNT_GET(x) (((uint32_t)(x) & GPU_GCREGFETCHCONTROL_COUNT_MASK) >> GPU_GCREGFETCHCONTROL_COUNT_SHIFT)

/* Bitfield definition for register: GCREGCURRENTFETCHADDRESS */
/*
 * ADDRESS (R)
 *
 * address
 */
#define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_MASK (0xFFFFFFFFUL)
#define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_SHIFT (0U)
#define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_GET(x) (((uint32_t)(x) & GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_MASK) >> GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_SHIFT)




#endif /* HPM_GPU_H */
